
.text
.global _start
_start:
@Address Exception Mode in Entry
@0x00000000 Reset                 Supervisor
reset_entry:
    b reset

@0x00000004 Undefined instruction Undefined
undef_instruction_entry:
    b undef_instruction_entry

@0x00000008 Software Interrupt    Supervisor
swi_entry:
    b swi_entry

@0x0000000C Abort (prefetch)      Abort
abort_prefetch_entry:
    b abort_prefetch_entry

@0x00000010 Abort (data)          Abort
abort_data_entry:
    b abort_data_entry

@0x00000014 Reserved              Reserved
reserved_entry:
    b reserved_entry

@0x00000018 IRQ                   IRQ
    b irq_entry @NOTE:when irq occured, svc's next pc instruction was filled to lr automaticly.

@0x0000001C FIQ                   FIQ
frq_entry:
    b frq_entry

reset:
    ldr sp, =1024 * 4
    bl close_watch_dog
    bl init_sdram
    bl copy_main_code_nand2sdram


	/*
	7  6  5  4  3  2  1  0
	I  F  T  1  0  0  1  0
	|  |  |  -------------
	|  |  |        |_Interupt Mode
	|  |  |_0:not Thumb mode
	|  |_1:disable Fast Interupt
	|_1:disable Interupt
	*/
    msr cpsr_c, #0xd2 @set to irq mode. cpsr_c is cpsr[0:7] bits
    ldr sp, =0x33000000 @0x30000000+16*1024*1024=0x32000000 -> 16M position as irq's stack. [0x33000000, 0x32000000) size:16M

    msr cpsr_c, #0xd3 @set to svc supervisor mode
    ldr sp, =1024 * 4


    bl init_irq
    msr cpsr_c, #0x53; @open Interupt by setting cpsr_c.I bit

    ldr sp, =0x34000000       @0x30000000+64*1024*1024 64M position   [0x3400000, 0x33000000) size:16M
    ldr lr, =halt_loop        @set return_address
    ldr pc, =main             @jump to main,run on sdram.

halt_loop:
    b halt_loop

irq_entry:
    sub lr, lr, #4 @calc lr, this lr is irq's lr,but the value is filled with svc mode's next instruction when irq occured.
    stmdb sp!, {r0-r12, lr}
    ldr lr, =irq_int_return
    ldr pc, =int_service

irq_int_return:
    ldmia sp!, {r0-r12, pc}^ @^ means irq's spsr copy to user_mode's cpsr



